============================================================== Guild: wafer.space Community Channel: 📐 - Designing / 🕰️-analog After: 2026-08-31 11:59 p.m. Before: 2026-10-01 12:00 a.m. ============================================================== [2026-09-01 4:07 p.m.] tholin Has anyone used the mimcap in an analog design before? [2026-09-01 4:36 p.m.] anfroholic These guys did, https://github.com/ishi-kai/ISHI-KAI_Multiple_Projects_WaferSapce-GF180-1 But don't know any of their handles, or even if they are here. {Embed} https://github.com/ishi-kai/ISHI-KAI_Multiple_Projects_WaferSapce-GF180-1 GitHub - ishi-kai/ISHI-KAI_Multiple_Projects_WaferSapce-GF180-1: IS... ISHI-KAI's Multiple Projects Wafer for Wafer.Sapce GF180 Run 1. - ishi-kai/ISHI-KAI_Multiple_Projects_WaferSapce-GF180-1 [2026-09-01 4:36 p.m.] tholin Also, why is it that whenever I do `calma` on a layout, it says "X problems occured." and these white things show up? It doesn’t happen if I first flatten the layout. {Attachments} 2026-09_media/image-0860C.png [2026-09-01 4:36 p.m.] tholin I don’t know if the resulting GDSII is usable [2026-09-01 4:36 p.m.] anfroholic That's all I got, sorry [2026-09-01 6:24 p.m.] tholin Now I can’t even extract without warnings. I wanna know how to view those. {Attachments} 2026-09_media/image-BD5CB.png [2026-09-01 6:54 p.m.] 246tnt feedback save xxx.txt. iirc [2026-09-01 8:17 p.m.] tholin Oh, magic is doing a weird without generating a warning. The `calma` command generates this outcropping of nplus that is not present in any way in the mag file, causing DRC errors. {Attachments} 2026-09_media/image-785F0.png [2026-09-01 8:44 p.m.] 246tnt The gf180mcu tech file is definitely not perfect. NPLUS and PPLUS have weird rules about overlap when near the limit of nwell but I always managed to tweak the mag to get valid output. [2026-09-02 9:50 a.m.] tholin And after all the subcircuits, it simply boils down to this {Attachments} 2026-09_media/image-B498A.png [2026-09-02 9:52 a.m.] tholin Having an overtemperature shutdown that turns off if it just gets vaguely "too hot" would be nice, but that’s about it. [2026-09-02 12:09 p.m.] tholin {Attachments} 2026-09_media/image-C34A7.png [2026-09-02 3:03 p.m.] tholin Huh {Attachments} 2026-09_media/image-43B58.png [2026-09-02 3:03 p.m.] tholin Might be okay? [2026-09-02 3:39 p.m.] 246tnt Yeah not unexpected. If DRC passed it's fine [2026-09-03 3:29 p.m.] tholin I’ve been doing nothing but layout for three days {Attachments} 2026-09_media/image-EDDEA.png 2026-09_media/image-D0AAF.png 2026-09_media/image-24BDC.png 2026-09_media/image-1A6A3.png 2026-09_media/image-EF3F1.png 2026-09_media/image-191BF.png 2026-09_media/image-84422.png 2026-09_media/image-4B641.png [2026-09-03 3:30 p.m.] tholin All building up to this. This is the circuit that I showed before, that generates 4 reference voltages and then has an analog multiplexer to choose one with two digital inputs. {Attachments} 2026-09_media/image-513F7.png [2026-09-03 3:31 p.m.] tholin Zoom-in on the analog multiplexer {Attachments} 2026-09_media/image-70F58.png {Reactions} 👀 💜 [2026-09-03 4:00 p.m.] tholin I keep having troubles with the diode models! {Attachments} 2026-09_media/image-A86EE.png [2026-09-03 4:58 p.m.] tholin Its specifically D2 here {Attachments} 2026-09_media/image-30C84.png [2026-09-03 6:16 p.m.] tholin The other time I’ve had trouble with the diode models was *also* a resistor and diode in series... [2026-09-03 6:43 p.m.] 246tnt What are the diode for ? [2026-09-03 10:26 p.m.] tholin Update: got it working {Attachments} 2026-09_media/image-27BE5.png [2026-09-03 10:26 p.m.] tholin This is from simulating the extraced SPICE {Reactions} 💜 [2026-09-04 8:34 a.m.] archit3ch Are you also doing audio? Did that get anywhere? [2026-09-04 1:35 p.m.] mrmadbrain I've been doing lots of audio but on desktop in C++ finally {Reactions} 💙 [2026-09-04 2:10 p.m.] archit3ch Ahhh, I use Julia for desktop SPICE audio 😎 [2026-09-04 2:13 p.m.] mrmadbrain interesting choice :3 we have our own backend code rather than juce for doing vst/au/aax/clap plugins [2026-09-04 2:14 p.m.] archit3ch Do you work under a brand? [2026-09-04 2:15 p.m.] archit3ch I'm closer to 'custom assembly for the specific application' but Julia still plays a critical role. [2026-09-04 2:15 p.m.] mrmadbrain 3 people in our small company [2026-09-04 2:15 p.m.] mrmadbrain https://www.plogue.com/ {Embed} https://www.plogue.com/ Plogue | Music Software | Developers - Software Synth | Audio Engin... Plogue Art et Technologie, Inc. Makers of chipsounds, Bidule, chipspeech, chipsynth and many others. 2026-09_media/plogue_p310-E8F5D.png [2026-09-04 2:16 p.m.] archit3ch Wait, I know those guys. 🫡 [2026-09-04 2:16 p.m.] archit3ch I mean I've heard of you. [2026-09-04 2:17 p.m.] mrmadbrain lots of retro synths like FM and SNES and C64 emulation {Reactions} ❤️‍🔥 [2026-09-04 5:42 p.m.] namibj Why shouldn't you be able to increase the length of them? [2026-09-04 5:53 p.m.] namibj I don't think you want to go quite that long for your LDO; this has considerable minimum drop out at "full current" and not itself for thermal reasons, or viewed from the other direction: long channels for your main power pass FET beyond what's needed to be safe and reliable under years of sustained current would push the minimum pass resistance so high that you'd likely hit thermal limits for drop out voltage with the pass transistor gate fully-on, instead of needing to operate under gate-not-fully-on "active regulation" conditions to drop enough voltage at full sustained current for that `I × V = I² × R = Power` to hit TDP. You've got closed loop feedback control going on, the process variations of concern shouldn't matter much here, as long as all those fingers see the same usual voltage drop across them. [2026-09-04 5:53 p.m.] namibj That can be just on the source side abutted though, right? [2026-09-04 5:56 p.m.] tholin That’s not an option in the device generator [2026-09-04 5:56 p.m.] namibj Definitely make a script please for your bulk LDO pass pfet PCell! You want it easy to adjust afterwards! @tnt might have convenient macros for contact generation down to PCell power bars from orthogonal higher-layer aggregating metal PDN straps, as that's basically done on TinyTapeout from the PDN to the user content. [2026-09-04 5:57 p.m.] tholin Its not a PCell though [2026-09-04 5:58 p.m.] tholin I mean, I just used the `array` command in magic [2026-09-04 6:12 p.m.] jonahsaunders is there a question chat? [2026-09-04 6:16 p.m.] jonahsaunders Started a thread. [2026-09-04 7:09 p.m.] tholin So, if I try and run this simulation with the SPICE-extracted netlist of my power PFET array, it works for a while, until charging is completed. After a few us, current on V2 increases rapidly until it breaks the simulation ("timestep too small"), but the gate voltage remains at 5V and the capacitor doesn’t charge, so I don’t know where that energy is going. Is this a simulation oopsie or latchup? [2026-09-04 7:29 p.m.] tholin By "rapidly" I mean a straight horizontal line on the graph [2026-09-04 7:39 p.m.] namibj As long as mismatch modeling statistics say that all your fingers are under similar enough behavior under all the load-spreading-critical "[(supposed) safe (at full packaged IC level)] operating areas" such as to give good enough control (e.g. sense fingers bypassing into current sense resistors) and good enough thermal balancing, you're good. You can do fairly analytical handling of the mismatch modeling equations for the FETs. Sadly for economic numerical modeling we'd need the tricks that use sensitivity calculations to massively boost sample efficiency for the monte carlo sampling, by essentially asking the simulator how meaningless any given random variable that's monte-carlo'd is for the output measure under investigation (e.g. some quantified thermal balancing). Also do keep in mind that _if_ you do conform your pad ring to the limitations/restrictions of the ACF flip chip bonding we're testing with `FC01` (which btw. are not incompatible with performing the classic COB wedge bonding that was done to your accidentally-self-melting-DAC chip): you could use dual-sided heat sink attachment through thin polyimide and ACF on top and the thinned silicon substrate on the back, and further exploit the current handling capability of the much larger attachment opportunity if you use some extra/bonus high-current pads formed from top metal over the power FET ("circuit under pad"). https://acffilm.com/acf-film.html#acf-cof E.g. "TCF7040/41 Series" () seems to be specified for minimum pad area of 1500 μm² and min pad space is 15μm and from what I understand claims <1Ω contact resistance (I'm assuming for a minimum nominal contact; at a 50A/mm² max current density claimed in the datasheet of `AC-7206U-18`, that'd be <75 mV and <3.75 W/mm² (from contact ohmic heating alone, at such upper-limit levels of current density))... Don't worry our bond pads are not too small for ACF to work with decent reliability (like, IIRC in practice over 2 nines of yield per foundry pad ring sized bond pad if a small pillar/bump/column is formed; the tape is 10~30~50 μm thick and the bumps need to be a large fraction but less than the thickness of the tape), just the classic chip on flex formulations aren't targeting pad sizes that are closer to face-to-face chip-to-chip bonding (e.g. non-silicon photodiode array or even silicon based avalanche photo diode array, directly bonded to a small-process-node readout ASIC in a "normal [Bi]CMOS process") than purpose designed top metal pads for commodity flex-PCB-DesignForManufacturability. {Embed} https://acffilm.com/acf-film.html Telephus ACF Anisotropic Conductive Film | Tape Telephus ACF Product overview - FPC, PCB, LCD, ITO Glass, FR4, COG, COF, COB, FOF, COP [2026-09-04 7:59 p.m.] namibj ...... Hmmm...... I have an idea, if you can have one precision (I think 1% should suffice) resistor (e.g. off-chip) to set the over temp threshold, a simple or if you already have a voltage reference, just a plain diode wired almost-parallel with the off-chip resistor (they share _separate_ precision poly resistor array resistors; threshold is when the voltage across the diode drops below the voltage across the resistor; the poly resistor array gives you two pretty-identical resistors to provide practically-identical biasing conditions)). Let me draw that up real quick if I can get my computer's internet back to "properly working"; or upon request with pen & paper if I'm failing/too slow to fix computer. Principle is that an off-die resistor can easily provide a decent tolerance if compared to a "proportional to absolute temperature" diode/bandgap thermal sense that nicely fits right besides a thermal hotspot on the die. [2026-09-04 8:05 p.m.] namibj Might be xschem rounding error not actually joining them despite it looking joined to the eye. You can use the hotkey for snap-to-connection-point to focus on the two symbol's pins, then drag out to the middle of nowhere to a grid aligned spot, taking care to draw both parts starting from the symbol's pin and ending at the shared location in the middle of nowhere. Use the "highlight connected net" (iirc `k`) action on both parts to verify they're now connected. If it then works without complaint you know it was the error and can try to snap all associated drawings in the schematic to grid, and clean the "wire excursion to the middle of nowhere" up. [2026-09-04 8:09 p.m.] tholin It seems to have just kinda fixed itself? [2026-09-04 8:10 p.m.] namibj AFAIK latchup isn't modeled in the extraction/SPICE, at least for the MOSFETs; can you share me the two SPICE situations (normal vs. PEX) so I can look? [2026-09-04 8:15 p.m.] namibj One major thing to consider is what absolute and relative tolerances are set for the solver; the power FET might be a bit out of typical scale and thus could reasonably trip convergence warning thresholds like that from attempting to go for whatever time steps make it's time discretisation originating approximation error small enough to meet the target tolerance.... despite handling currents FAR larger than what the config defaults of the PDK are actually good for. [2026-09-04 8:32 p.m.] tholin {Attachments} 2026-09_media/control_bench-095E0.spice [2026-09-04 8:34 p.m.] tholin {Attachments} 2026-09_media/control_bench-F19B0.spice [2026-09-04 8:35 p.m.] tholin I think you can tell which is which by the filesize [2026-09-04 8:35 p.m.] tholin Delete the include referencing a "power_fet_f" on the first file [2026-09-04 9:16 p.m.] namibj https://www.falstad.com/s.php?s=JDLNxt {Attachments} 2026-09_media/circuit-20260904-2116-0F27C.png [2026-09-04 9:37 p.m.] namibj At least I think that's the way described above. Basically that. Or approximately that. Diode has as far as I understand it about `-2 mV/K` temperature dependence under vaguely constant current conditions. So a +- 5 K tolerance for the trip point would only need +-10 mV performance from the comparator and the reference used by said comparator. I'm not _sure_ but I'd definitely throw the idea of using polyfuses to "remember" a reference "room temperature" and set it up to trip at "room temperature +100C" or maybe "room temperature +75C" for 150/125 degrees Celsius Tj_max self-limiting. E.g. crank the external set resistor from nominal until it trips the mechanism at room temp, then calculate the fuse code for it; or set it up as a shift register to first just feed dynamically to do binary search for what code makes it trip at room temp, and write that; or perhaps literally use a hot box kept at like 115C with a fan force-cooling the chip to near ambient, and do the binary search under those conditions. In any case, I'd assume there's easy-to-port temperature sensor IP you could readily harness and easily add some such factory calibration/zeroing block to. If it's some kind of digital temperature sensor mechanism, and the temperature sense core itself doesn't depend on a clock, it's probably quite easy to figure out how to plonk it down next to a simple DAC in front of a comparator so that this very DAC could be set to whatever code (+nominal offset that only assumes the scale isn't far off in temp co) trips it under factory conditions. This doesn't _have to_ be done by external hardware, it could be done on-die at first power-up from just feeding good power and then strapping into factory-cal mode, shouldn't even need a separate clock could just use a fairly trashy ring osc with heavy divider. [2026-09-04 11:16 p.m.] tholin It doesn’t do the current increase anymore, but still crashes. Considering the SPICE-extracted netlist has no parasitics and is just several thousand PFETs in parallel between the same two pins, I do believe this to be a simulation problem. [2026-09-04 11:40 p.m.] namibj Try Xyce if you don't do anything too fancy in ngspice [2026-09-04 11:41 p.m.] namibj (it's supposedly rather suited to large extracted circuits) [2026-09-04 11:42 p.m.] namibj if they're literally identical you can optimize by replacing a bunch with just the `m` multiple parameter instead of physical duplicates. I'm surprised your extraction doesn't do that already for you. [2026-09-04 11:43 p.m.] namibj (I'm sorry it's been one and a half weeks since I had my desktop with working browser/internet, just phone in the meantime, I miss-estimates how much I'm "busy" catching up with various things..... won't get to too much spice reading today 🙁 ) [2026-09-05 12:00 a.m.] tholin I wonder what the chances are of Xyce being able to simulate the whole chip for a few us... [2026-09-05 1:32 a.m.] namibj do you have any oscillators on there? [2026-09-05 1:35 a.m.] namibj if not, then I'm highly confident it can, in part because it can readily adjust step size as appropriate. Thus it'd actually be pretty "free" to just go to several seconds worth of "steady state" solution from a transient start. [2026-09-05 1:37 a.m.] namibj well, not fully free, it'd still be like a hundred or a couple hundred time steps to go from transistor fT limited waveform fidelity needs up to multi-second scale, without just fast-forwarding over anything notable, but otherwise.... [2026-09-05 1:40 a.m.] namibj Xyce is half made for that, and the other half to do non-public rad hard model sim for US nuclear and space stuffs. It's just that the base framework stuff is easy to keep separate from the modules that contain the spicy stuff that has export restrictions on it, and the us gov labs are generally quite happy to share code/software if it's science stuff that's like base frameworks/tooling. [2026-09-05 1:45 a.m.] namibj in vaguely related spirits, https://sam.nlr.gov/ and https://github.com/stanfordhpccenter/HTR-solver {Embed} https://sam.nlr.gov/ Welcome - System Advisor Model - SAM The System Advisor Model (SAM) is a performance and financial model designed to estimate the cost of energy for grid-connected power projects. {Embed} https://github.com/stanfordhpccenter/HTR-solver GitHub - stanfordhpccenter/HTR-solver: Hypersonic Task-based Resear... Hypersonic Task-based Research (HTR) solver for the Navier-Stokes equations at hypersonic Mach numbers including finite-rate chemistry for dissociating air and multicomponent transport. - stanfordh... 2026-09_media/HTR-solver-AC059 [2026-09-05 1:53 a.m.] namibj SAM does history-mapped simulation of PV and PV+battery systems under most grid-tie models including financial aspects relevant in the US; also other energy sources but primarily solar and obviously focused (these days) on PV. HTR-solver does supersonic and hypersonic flow for you including notably (finite rate!) chemical reactions you're gonna catch when you superheat stuff like air. I think but am not sure it can actually do a rocket nozzle (liquid bipropellant, the injector, chamber, and then the nozzle itself) but never got around to reeeealy check/confirm. Certainly should be able to model the deflagration to detonation transition of a fuel/air gas mix in a hose/tube (the tamer ones are quite an eye catcher "fuse" for a potato cannon or the like if done with e.g. propane in clear pvc hose). And ofc actual normal aerodynamics that may or may not involve supersonic flow. It's written in Regent, based on Terra, based on (largely, though not _exclusively_ LuaJIT 😄 (SAM is boring from the software implementation side afaik.) [2026-09-05 2:34 p.m.] tholin I’m still not sure why any of the opamps I’ve built so far are incapable of being used as voltage followers. Simulations when I wire them up as such always terminate with "timestep too small" [2026-09-05 2:34 p.m.] tholin Oh well [2026-09-05 2:35 p.m.] tholin Chaining two inverting amplifiers with a gain of 1 has served me well so far [2026-09-05 2:47 p.m.] tholin My previous version of the PFET controller looked like this, but this is kinda problematic. The DISABLE input is digital. It fully turns off the PFETs if high, and is fed from a comparator that compares the battery voltage to the cutoff voltage. But this WILL end up oscillating as the battery nears fully charged, even with hysteresis added. [2026-09-05 2:47 p.m.] tholin So, new version, where DISABLE can actually be an analog signal {Attachments} 2026-09_media/image-E00E8.png [2026-09-05 2:48 p.m.] tholin Now if I replace the comparator in the control circuit with an opamp, I should have something closer to an actual voltage regulator. [2026-09-05 2:48 p.m.] tholin This new circuit essentially just produces an analog `max` between all its inputs [2026-09-05 2:48 p.m.] tholin With one input being the current reference [2026-09-05 2:52 p.m.] tholin Three inputs: current reference analog voltage limiter digital disable if the thing needs to be off entirely right now (i.e. charge complete, overtemperature) {Attachments} 2026-09_media/image-5F9BB.png [2026-09-05 3:06 p.m.] tholin I hate diodes I hate diodes I hate diodes I hate diodes {Attachments} 2026-09_media/image-8A196.png [2026-09-05 3:09 p.m.] 246tnt Why are you using them then ... [2026-09-05 3:12 p.m.] tholin What else am I supposed to do? [2026-09-05 3:35 p.m.] tholin The docs reference another two types of diodes in the PDK, but magic doesn’t have device generators for those, so I’d be on my own. {Attachments} 2026-09_media/image-F6700.png [2026-09-05 3:44 p.m.] tholin I can’t think of a way to re-design this circuit to not use diodes [2026-09-05 4:02 p.m.] tholin Anyways. Current approach works. There is still a little bit of oscillation, but its not as bad as it looks. I’d like to get rid of it, but.... yeah, simulation crashes make debugging this hard right now. {Attachments} 2026-09_media/image-A92A3.png 2026-09_media/image-28A06.png [2026-09-05 4:02 p.m.] tholin Last thing to do is to detect when charging is *actually* done [2026-09-05 4:03 p.m.] tholin For which I might actually be able to use a shunt. I just need to detect that the current through the PFETs is nearing zero. [2026-09-05 4:17 p.m.] namibj ....what inputs are you feeding them? [2026-09-05 4:18 p.m.] namibj if there are piece wise linear input sources in the netlist, I suggest to use Xyce it automatically inserts breakpoints for the integrator to split cleanly at these discontinuities. [2026-09-05 4:20 p.m.] namibj iirc my LiFePO4 charger LDO chips I've put onto the radio swarm boards use a cutoff of iirc 1% of what teh current limit is set to; and 10% when starting from deep discharge regions of voltage; might have mixed the two numbers up though I'd have to look at the datassheet to confirm. [2026-09-05 4:21 p.m.] namibj both should be ok though, especially the 10% cutoff for end of charge detection [2026-09-05 4:22 p.m.] tholin I’m not sure I can use Xyce from inside xschem [2026-09-05 4:22 p.m.] namibj you can [2026-09-05 4:22 p.m.] namibj it works like the same [2026-09-05 4:22 p.m.] namibj just the `.control` section is done differently [2026-09-05 4:23 p.m.] namibj it's a menu swap [2026-09-05 4:23 p.m.] namibj like, in the simulator setup menu you select xyce [2026-09-05 4:25 p.m.] namibj show me your `.control` section real quick and I'll tell you if I can just quickly try that for you after dinner [2026-09-05 4:27 p.m.] tholin {Attachments} 2026-09_media/image-6A69E.png [2026-09-05 4:32 p.m.] namibj good I can port that that's like just save all and rawfile and the tran itself [2026-09-05 4:32 p.m.] namibj `baser` is what? [2026-09-05 4:33 p.m.] tholin Its an old thing I no longer need. My control is actually this. {Attachments} 2026-09_media/image-0FB1C.png [2026-09-05 4:33 p.m.] tholin I actually forgot what the method=gear is about. If I remove it, the simulation takes a lot longer to run and the current reference behaves completely differently. [2026-09-05 6:03 p.m.] namibj it's the integrator's predictor; iirc this is actually a sign your current reference is broken and an oscillator [2026-09-05 6:03 p.m.] namibj honestly [2026-09-05 6:05 p.m.] namibj try if it fixes if you just add a fat chunk of decoupling RC to it, just ideal. I'm going to have to apologize I won't get into the headspace for making this port proper before I catch some sleep, but I'll do it early tomorrow, well, around noon berlin time should be it. [2026-09-05 6:17 p.m.] tholin ...oh! {Attachments} 2026-09_media/image-C2C7C.png [2026-09-05 6:42 p.m.] namibj ....did I fix it? [2026-09-05 6:47 p.m.] tholin You were right that the current reference was oscillating [2026-09-05 6:47 p.m.] tholin I fixed it by making the output stage of the opamp larger [2026-09-05 6:47 p.m.] tholin It was having trouble driving its output [2026-09-05 6:48 p.m.] tholin x1 [2026-09-05 7:02 p.m.] namibj if there's a repo or something tomorrow I could update/swtich to Xyce I'd be up to try that fyi, like, after I'm done sleeping. [2026-09-05 8:16 p.m.] tholin I think I finally perfected this circuit. Here you see it start with constant current charging, then switch to constant voltage, then turn off once the charge current drops to near zero. {Attachments} 2026-09_media/image-DE901.png [2026-09-05 8:16 p.m.] tholin The green line is the actual voltage of the capacitor being charged [2026-09-05 8:17 p.m.] tholin Yellow is what it sees on the BAT output of the chip [2026-09-05 8:17 p.m.] tholin It is oscillating, but this actually behaves better in every way than when I actively try to dampen the oscillations, which always just makes it oscillate MORE or crash the simulation. [2026-09-05 8:18 p.m.] tholin The resulting circuit is a mess, but its *my* mess and I love it {Attachments} 2026-09_media/image-C3D7A.png [2026-09-05 8:19 p.m.] tholin The circuit to sense the charge current being low is... interesting, but it works [2026-09-05 8:21 p.m.] tholin There is an S/R latch that is reset whenever the voltage at BAT is roughly 10% below the charge cutoff reference and set when the charge current is detected to be low. [2026-09-05 8:23 p.m.] tholin I’m not sure how well the low current detection is going to work, so a digital input pin "LENb" can be used to disable the feature. In that case, the voltage regulator just keeps running and holds BAT at the cutoff voltage continuously. [2026-09-05 8:24 p.m.] tholin The "CE" input pin allow charging to be disabled whenever [2026-09-05 8:25 p.m.] tholin The three resistors and diode you see at the top right just serve to pull the power PFETs gates high if the battery is inserted but power to the charger is disconnected. [2026-09-05 8:27 p.m.] tholin I got a pull-up and pull-down generator because the digital IO pads require all the settings inputs to be set to something. [2026-09-05 8:28 p.m.] tholin I got an unused output [2026-09-05 8:52 p.m.] tholin And then this is the overdischarge protection circuit, also with a programmable cutoff. This one’s real simple. {Attachments} 2026-09_media/image-520EC.png [2026-09-05 8:53 p.m.] tholin {Attachments} 2026-09_media/image-A4DB9.png [2026-09-05 9:38 p.m.] namibj way too much oscillation tho [2026-09-05 9:39 p.m.] namibj have you ever found out how to chase I and V plots to hunt down where oscillation loops happen? [2026-09-05 9:41 p.m.] namibj I see purple and `PU` are the same net here; that's gonna extract horribly to spice, just to be aware [2026-09-05 9:41 p.m.] namibj though your hierarchical digital experiences should have taught you that already [2026-09-05 10:33 p.m.] tholin Not much I can do about that. Would love to get rid of it, but the simulation crashes when I try. [2026-09-05 10:35 p.m.] tholin Here we are: https://github.com/AvalonSemiconductors/ws-charge-controller {Embed} https://github.com/AvalonSemiconductors/ws-charge-controller GitHub - AvalonSemiconductors/ws-charge-controller: AIO charge cont... AIO charge controller and overdischarge protection IC for Li+, LiFePo, LTO and Na+ cells on wafer.space gf180mcu - AvalonSemiconductors/ws-charge-controller 2026-09_media/ws-charge-controller-6F0E3 {Reactions} ❤️ (2) [2026-09-05 10:35 p.m.] tholin All the action is happening in analog/ right now [2026-09-07 9:11 a.m.] mithro_ @namibj - The Julia people had some type of alternative engine for spice solving that they open sourced at some point. [2026-09-07 9:42 a.m.] namibj Yeah I've seen [2026-09-07 9:47 p.m.] tholin Any luck yet with getting my control circuit to simulate in Xyce? [2026-09-07 9:48 p.m.] tholin Its still crashes in ngspice, making it impossible for me to try and get rid of the oscillation. [2026-09-08 12:51 a.m.] namibj I'm sorry for the delays; I do have hope for tomorrow noon-ish based on the weather forecast saying it's gonna be decently comfy [2026-09-08 12:52 a.m.] namibj It should though I'm fairly confident it will. [2026-09-08 12:49 p.m.] namibj good news: I've got the container running and PDK set to gf180mcuD [2026-09-08 12:53 p.m.] tholin The container? You mean the nix shell? [2026-09-08 12:59 p.m.] namibj commit `3abac8518a4b802946efbb499cee2e6e946eb017` in my `tt_gf-0p3_mcml` repo (I'll fetch a link) , folder `xschem`, file `c4_type_8_to_1_tb.sch`, is set up to use Xyce to generat e arawfile. [2026-09-08 1:00 p.m.] namibj I'll take that as refereence right after I fetch a link to the commit (or if there's none yet, ensure it's on github and then get that link) and do a corresponding patch to your `control_bench.sch`, if that's ok, @Tholin ? [2026-09-08 1:01 p.m.] namibj The Xyce probably isn't (properly) in that 🙁 [2026-09-08 1:01 p.m.] namibj I have the IIC-OSIC container set up for the IHP Chipalooza related works of the high speed serdes [2026-09-08 1:01 p.m.] tholin It isn’t, but I got it installed on my machine through AUR [2026-09-08 1:02 p.m.] namibj that we'll port to sky130A and then backport to gf180mcuD [2026-09-08 1:02 p.m.] tholin Yep, go ahead [2026-09-08 1:03 p.m.] namibj yeah good I have it through arch mechanisms as well I can test with that in your shell once I have xschem doing things that work in the container at least [2026-09-08 1:03 p.m.] namibj like, as mentioned, I have it _working right now_ on my project's testbench [2026-09-08 1:03 p.m.] namibj {Attachments} 2026-09_media/image-E1F55.png [2026-09-08 1:03 p.m.] namibj note the ngspice parts being commented-out and the waveforms loaded [2026-09-08 1:03 p.m.] namibj I manually deleted the rawfile and reran sim to check btw [2026-09-08 1:04 p.m.] namibj (and between those two, manually cleared the waves in xschem) [2026-09-08 1:08 p.m.] namibj https://github.com/namibj/tt_gf-0p3_mcml/commit/91583ac881daf6744508e5ba43aca38b421dd477 {Embed} https://github.com/namibj/tt_gf-0p3_mcml/commit/91583ac881daf6744508e5ba43aca38b421dd477 Bypassed clk_buf in the DIV2's latch-loop-closure. Testing imminent... 2026-09_media/91583ac881daf6744508e5ba43aca38b421dd477-1514F [2026-09-08 1:11 p.m.] namibj @Tholin Can you take that, `cd` into the xschem directory or just copy that folder over to your nix shell's influence, open the above mentioned testbench, and then in the xschem menu "simulation"->"configure simulators and tools"->{check "Xyce batch" in "spice", it should read `Xyce "$N"`} ? [2026-09-08 1:23 p.m.] tholin Not until I’m home [2026-09-08 1:35 p.m.] namibj put this in `analog/xschem/simulation/`, then cd there, then run `Xyce control_bench.spice`. {Attachments} 2026-09_media/control_bench-1A650.spice [2026-09-08 1:35 p.m.] namibj @Tholin Something is whining about no model card for a pfet_06v0 device [2026-09-08 1:35 p.m.] namibj oh ok [2026-09-08 1:47 p.m.] namibj I made `XM2` in approx also m=792 instead of it's m=726 as you had; I also set to divide the written `w` through `m`. [2026-09-08 1:51 p.m.] tholin m is supposed to be how many parallel transistors there are [2026-09-08 1:51 p.m.] tholin Do not divide w by m [2026-09-08 1:52 p.m.] 246tnt Wait wait ... `m` is the multiplier. `n` is the number of finger. If you have `m=2` and `W=10u` then the effective width is `20u`. [2026-09-08 1:53 p.m.] 246tnt If you have `n=2` and `W=10u` then it's a single 2 finger transistor and the effective width is `10u` because `W` is the W of all the fingers. [2026-09-08 2:41 p.m.] namibj @Tholin here ya go {Attachments} 2026-09_media/Xyce-patch-v1-05C8C.patch [2026-09-08 2:42 p.m.] namibj {Attachments} 2026-09_media/image-56986.png [2026-09-08 2:42 p.m.] namibj {Attachments} 2026-09_media/power_fet_approx-1E140.png [2026-09-08 2:43 p.m.] namibj it did not like an `nf=10 l=2u w=467.2u` `pfet_06v0`. [2026-09-08 2:44 p.m.] namibj Also I was primarily requested to enable Xyce for it as Xyce has _substantial_ amounts of tuning knobs and fancy fallbacks to use when convergence issues are encountered in more traditional Spice flows like you'd have with ngspice. [2026-09-08 2:46 p.m.] namibj Yeah I know that's what I assumed the spec kinda asked for.... though given the power pass fet case of battery charger and it occupying a good chunk of a half slot I have a feeling it legit meant to be 800um by 500um [2026-09-08 2:46 p.m.] namibj (of a gigantic finger array) [2026-09-08 2:47 p.m.] namibj I'll have to jump and fetch my preordered bread before they close so be back in a bit, and only on phone in the meantime. [2026-09-08 2:48 p.m.] namibj you should be able to just run `git apply` on the repo btw to apply the patch. [2026-09-08 2:48 p.m.] namibj well, `git apply Xyce-patch-v1.patch`. Make sure it's on the correct clean git commit! [2026-09-08 2:49 p.m.] namibj I admit I slightly changed the setting for the time thingy [2026-09-08 2:50 p.m.] namibj err, the pulse's length and period, that got the breakpoints and such more functional for xyce shomehow but that's not necessary other dials can do what this did to unlcok convergence, so that sim with the "correct/desired" time would work. [2026-09-08 2:50 p.m.] namibj i'll see sooon [2026-09-08 5:57 p.m.] namibj yeah looks very robust now [2026-09-08 5:58 p.m.] namibj adjusted some of them time integration and nonlinearsolver-tran options to be more _robust_ [2026-09-08 5:58 p.m.] namibj at expense of happy-case speed [2026-09-08 5:59 p.m.] namibj let's see {Attachments} 2026-09_media/image-A9CCB.png [2026-09-08 5:59 p.m.] namibj a full second with 1u max timestep enforcement, back to the enable pattern you had before [2026-09-08 5:59 p.m.] namibj (500 Hz, 50% duty cycle) [2026-09-08 6:02 p.m.] namibj I'll run it in the background and probably get back to trying to fix the oscillation behavior later after seeing about how to make it use the extracted power FET in place of this... well, not _quite_ but rather first figuring out how to aggregate them into `m` as far as they happen to be identical fingers [2026-09-08 6:04 p.m.] namibj ``` 264 X1 BAT GATE DVDD DVDD pfet_06v0 ad=12.1472p pd=47.24u as=12.1472p ps=47.24u w=46.72u l=2u 66 X1 BAT GATE DVDD DVDD pfet_06v0 ad=12.1472p pd=47.24u as=20.5568p ps=94.32u w=46.72u l=2u 2376 X1 BAT GATE DVDD DVDD pfet_06v0 ad=12.1485p pd=47.245u as=12.1485p ps=47.245u w=46.725u l=2u 594 X1 BAT GATE DVDD DVDD pfet_06v0 ad=12.1485p pd=47.245u as=20.559p ps=94.32999u w=46.725u l=2u 264 X1 BAT GATE DVDD DVDD pfet_06v0 ad=16.3137p pd=63.265u as=16.3137p ps=63.265u w=62.745u l=2u 66 X1 BAT GATE DVDD DVDD pfet_06v0 ad=16.3137p pd=63.265u as=27.6078p ps=0.12637m w=62.745u l=2u 264 X1 BAT GATE DVDD DVDD pfet_06v0 ad=16.8948p pd=65.5u as=16.8948p ps=65.5u w=64.98u l=2u 66 X1 BAT GATE DVDD DVDD pfet_06v0 ad=16.8948p pd=65.5u as=28.5912p ps=0.13084m w=64.98u l=2u 264 X1 BAT GATE DVDD DVDD pfet_06v0 ad=19.8679p pd=76.935u as=19.8679p ps=76.935u w=76.41499u l=2u 66 X1 BAT GATE DVDD DVDD pfet_06v0 ad=19.8679p pd=76.935u as=33.6226p ps=0.15371m w=76.41499u l=2u 264 X1 BAT GATE DVDD DVDD pfet_06v0 ad=19.8796p pd=76.98u as=19.8796p ps=76.98u w=76.46u l=2u 66 X1 BAT GATE DVDD DVDD pfet_06v0 ad=19.8796p pd=76.98u as=33.6424p ps=0.1538m w=76.46u l=2u 1848 X1 BAT GATE DVDD DVDD pfet_06v0 ad=19.8809p pd=76.985u as=19.8809p ps=76.985u w=76.465u l=2u 462 X1 BAT GATE DVDD DVDD pfet_06v0 ad=19.8809p pd=76.985u as=33.6446p ps=0.15381m w=76.465u l=2u 264 X1 BAT GATE DVDD DVDD pfet_06v0 ad=19.8822p pd=76.99u as=19.8822p ps=76.99u w=76.47u l=2u 66 X1 BAT GATE DVDD DVDD pfet_06v0 ad=19.8822p pd=76.99u as=33.6468p ps=0.15382m w=76.47u l=2u 264 X1 BAT GATE DVDD DVDD pfet_06v0 ad=19.8952p pd=77.04u as=19.8952p ps=77.04u w=76.52u l=2u 66 X1 BAT GATE DVDD DVDD pfet_06v0 ad=19.8952p pd=77.04u as=33.6688p ps=0.15392m w=76.52u l=2u 264 X1 DVDD GATE BAT DVDD pfet_06v0 ad=12.1472p pd=47.24u as=12.1472p ps=47.24u w=46.72u l=2u 2376 X1 DVDD GATE BAT DVDD pfet_06v0 ad=12.1485p pd=47.245u as=12.1485p ps=47.245u w=46.725u l=2u 264 X1 DVDD GATE BAT DVDD pfet_06v0 ad=16.3137p pd=63.265u as=16.3137p ps=63.265u w=62.745u l=2u 264 X1 DVDD GATE BAT DVDD pfet_06v0 ad=16.8948p pd=65.5u as=16.8948p ps=65.5u w=64.98u l=2u 264 X1 DVDD GATE BAT DVDD pfet_06v0 ad=19.8679p pd=76.935u as=19.8679p ps=76.935u w=76.41499u l=2u 264 X1 DVDD GATE BAT DVDD pfet_06v0 ad=19.8796p pd=76.98u as=19.8796p ps=76.98u w=76.46u l=2u 1848 X1 DVDD GATE BAT DVDD pfet_06v0 ad=19.8809p pd=76.985u as=19.8809p ps=76.985u w=76.465u l=2u 264 X1 DVDD GATE BAT DVDD pfet_06v0 ad=19.8822p pd=76.99u as=19.8822p ps=76.99u w=76.47u l=2u 264 X1 DVDD GATE BAT DVDD pfet_06v0 ad=19.8952p pd=77.04u as=19.8952p ps=77.04u w=76.52u l=2u 66 X1 DVDD GATE BAT DVDD pfet_06v0 ad=20.5568p pd=94.32u as=12.1472p ps=47.24u w=46.72u l=2u 594 X1 DVDD GATE BAT DVDD pfet_06v0 ad=20.559p pd=94.32999u as=12.1485p ps=47.245u w=46.725u l=2u 66 X1 DVDD GATE BAT DVDD pfet_06v0 ad=27.6078p pd=0.12637m as=16.3137p ps=63.265u w=62.745u l=2u 66 X1 DVDD GATE BAT DVDD pfet_06v0 ad=28.5912p pd=0.13084m as=16.8948p ps=65.5u w=64.98u l=2u 66 X1 DVDD GATE BAT DVDD pfet_06v0 ad=33.6226p pd=0.15371m as=19.8679p ps=76.935u w=76.41499u l=2u 66 X1 DVDD GATE BAT DVDD pfet_06v0 ad=33.6424p pd=0.1538m as=19.8796p ps=76.98u w=76.46u l=2u 462 X1 DVDD GATE BAT DVDD pfet_06v0 ad=33.6446p pd=0.15381m as=19.8809p ps=76.985u w=76.465u l=2u 66 X1 DVDD GATE BAT DVDD pfet_06v0 ad=33.6468p pd=0.15382m as=19.8822p ps=76.99u w=76.47u l=2u 66 X1 DVDD GATE BAT DVDD pfet_06v0 ad=33.6688p pd=0.15392m as=19.8952p ps=77.04u w=76.52u l=2u ``` [2026-09-08 6:05 p.m.] namibj number of instances of that exact finger is up front, haven't yet scripted that into `m` as I might wanna also deduplicate across the `BAT GATE DVDD` vs. `DVDD GATE BAT`. [2026-09-08 6:06 p.m.] namibj which isn't the most trivial due to `ad`/`pd` and `as`/`ps` being specific to drain and source respectively. Still not hard to bulk edit though. [2026-09-08 6:07 p.m.] namibj `rg -e '^X[0-9]+ ' -r 'X1 ' extracted/power_fet_f.spice | sort | uniq -c` [2026-09-08 6:34 p.m.] tholin I don’t think it likes me {Attachments} 2026-09_media/image-FBC4C.png [2026-09-08 6:55 p.m.] tholin But this works [2026-09-08 6:55 p.m.] tholin I get an identical view as this screenshot [2026-09-08 6:59 p.m.] tholin Oh, the power_fet_approx was not updated correctly, it seems? [2026-09-08 6:59 p.m.] tholin I applied the changes manually [2026-09-08 6:59 p.m.] tholin I think its doing something [2026-09-08 6:59 p.m.] tholin I’m pinned at 100% CPU usage [2026-09-08 7:00 p.m.] tholin But those changes also break the simulation [2026-09-08 7:00 p.m.] tholin I’m not sure why you changed m on one of them either [2026-09-08 7:01 p.m.] tholin Those values were based off of what I have in the magic layout [2026-09-08 7:01 p.m.] tholin As you saw, the magic SPICE extraction has thousands of individual pfet devices. I just compressed that into two symbols with a high `m` [2026-09-08 7:01 p.m.] tholin Because of how I broke the transistors up horizontally, those values were all correct [2026-09-08 7:07 p.m.] tholin I can pretend to Xyce that the FETs are smaller by dividing their widths by 10 and multiplying `m` by 10 {Attachments} 2026-09_media/image-93ACE.png [2026-09-08 7:07 p.m.] tholin Its effectively the same thing [2026-09-08 7:08 p.m.] tholin What is happening there at the end? {Attachments} 2026-09_media/image-474FB.png [2026-09-08 7:09 p.m.] tholin Nothing should be happening anymore after charging completes [2026-09-08 7:09 p.m.] tholin CHRGb is a digital output too [2026-09-08 7:09 p.m.] tholin Btw, that point is where ngspice used to crash [2026-09-08 7:19 p.m.] tholin Okay, what happens is that the capacitor starts discharging again, causing x1.x3 to turn off. Now, this is expected and should have no side effects since the charge disable is latched. [2026-09-08 7:20 p.m.] tholin Yeah, nothing should happen as a result of this. No idea why CHRGb dips. [2026-09-08 7:22 p.m.] tholin If the diodes are leaky, this might be happening, actually {Attachments} 2026-09_media/image-619B8.png [2026-09-08 7:23 p.m.] namibj yeah trying this with 100m time now instead.... should I perhaps change the `CE` pulse source to have substantially less transients going on and thus allow larger time steps for covering long time spans with no high frequency activity? {Attachments} 2026-09_media/image-301FC.png [2026-09-08 7:24 p.m.] tholin CE should go high after a short delay and stay there for the entire simulation, unless you’re specifically testing it [2026-09-08 7:24 p.m.] tholin How are you getting a progress display? I just get xschem freezing until its done. [2026-09-08 7:26 p.m.] namibj IMO better do the extraction style with aggregation of identical fingers into `m`; much clearer overall and actually should be representative of physical reality because it _does_ cover true length (there are endcap effects going on, that's why it even matters what length they are set to for the sim). Maybe something something LVS-adjacent can get you such convenient aggregation even across the source/drain ambiguity? [2026-09-08 7:26 p.m.] namibj ahhhh ok I'll do that [2026-09-08 7:27 p.m.] namibj stopped; now gonna change the PULSE to stay on {Attachments} 2026-09_media/image-78A94.png [2026-09-08 7:27 p.m.] tholin Okay, diodes are definitely leaking current in the reverse [2026-09-08 7:27 p.m.] tholin Not sure how much or how to reduce it [2026-09-08 7:28 p.m.] tholin Going to put resistors in series with the diodes [2026-09-08 7:31 p.m.] tholin Redesigned the circuit a lil to have resistors in series with the diodes. [2026-09-08 7:42 p.m.] namibj trying 5.1ms long only now it started to get bogged down in time step size briefly after 5.01 ish [2026-09-08 7:42 p.m.] namibj don't have them [2026-09-08 7:42 p.m.] namibj ......ehhhh, what diodes, where do they come from/why are they even existing at all? [2026-09-08 7:43 p.m.] namibj call Xyce in terminal [2026-09-08 7:43 p.m.] namibj also what kind of machine setup do you have? I'll whip you up a reasonable match to my `mpirun` config to let it run on more than one core [2026-09-08 7:44 p.m.] namibj ``` (nice nice mpirun -np 2 --map-by package:hwtcpus:pe=15 Xyce -a control_bench.spice < /dev/null | tee ../Xyce_log_`date -Is | tr : _`.cat) & ``` this is what _I_ run [2026-09-08 7:45 p.m.] tholin In current_ref [2026-09-08 7:47 p.m.] namibj {Attachments} 2026-09_media/image-B80F8.png [2026-09-08 7:48 p.m.] namibj accidentally didn't have time correctly set tho 🙁 [2026-09-08 7:48 p.m.] namibj here ya go tho {Attachments} 2026-09_media/control_bench.raw-30A61.zst [2026-09-08 8:02 p.m.] namibj why are they so large? have you tried using shotkey ones instead perhaps? [2026-09-08 8:05 p.m.] tholin There is no device generator for shotkey diodes in magic [2026-09-08 8:05 p.m.] tholin So I’d be on my own [2026-09-08 8:09 p.m.] namibj Also, consider using current-sourcing-only (only pfet outputs, skipping the nfet's) for the drives of `current_ref`'s `CURREF`/`CTRL`/`DISABLE`. If you don't pull them low they don't leak (nearly as) much. [2026-09-08 8:10 p.m.] namibj well, not _sure_ about `CURREF` but the others probably don't need to be capable of sinking current given one of them is a comparator and the other literally just a CMOS buffer [2026-09-08 8:10 p.m.] namibj There is in Klayout [2026-09-08 8:15 p.m.] namibj but until junctions stop being acceptable, just use those [2026-09-08 8:16 p.m.] tholin ` [2026-09-08 8:16 p.m.] tholin `CTRL` is also intended to be analog [2026-09-08 8:16 p.m.] tholin Its just being driven by a comparator because that is generating less oscillations for some reason [2026-09-08 8:19 p.m.] namibj I'd go for diffusion-to-well diodes (nwell or lvpwell-in-dnwell, whichever is the one that gives the diodes the correct oreintation/polarity) with tiny fingers that are depending on reliability and how much current actually needs to be coped with either one or a small handful (up to like 6 or so I'd go without going for mathing the currents against the limits in the PDK docs for contacts, by feeling, trying to be fewer if vibes allow) of contacts to a single diffusion "finger" and multiple such fingers in the same well; with well taps on the outside and between these min-size diffusion fingers. [2026-09-08 8:22 p.m.] tholin They are p diffusion to nwell diodes [2026-09-08 8:22 p.m.] tholin I cannot generate the deep n-well ones because no magic device generators [2026-09-08 8:23 p.m.] namibj yeah just that 😄 [2026-09-08 8:23 p.m.] namibj the anode is which one again? p or n? [2026-09-08 8:25 p.m.] namibj right p is anode [2026-09-08 8:25 p.m.] namibj good [2026-09-08 8:25 p.m.] namibj literally then just p diffusion to nwell [2026-09-08 8:25 p.m.] namibj but like, make them share a single nwell [2026-09-08 8:26 p.m.] namibj well, if it matters that is, shouldn't change the leakage out of the anode but will affect the leakage from the cathode to the substrate [2026-09-08 8:32 p.m.] namibj ok I want you to try and reduce the power output control bandwidth _substantially_ by increasing the output impedance from the gate drive towards the large capacitance of the many gate fingers by a factor of 10 and if that still shows substantial oscillation another 10. I guess put a long enough poly resistor there [2026-09-08 8:33 p.m.] namibj I think the internals should be sufficciently more bandwidth than the power output in order to let the internals settle nicely prior to the output getting a chance to oscillate. [2026-09-08 8:37 p.m.] tholin The klayout sc diode has 686 DRC violations in magic {Attachments} 2026-09_media/image-8A401.png [2026-09-08 8:37 p.m.] tholin I think I just need to figure out how to draw one by hand [2026-09-08 8:41 p.m.] namibj There is a _chance_ that step-recovery and/or the directly related reverse recovery charge of those diodes are largely to blame for some interacting oscillation behavior between the 3 anodes; shottkey diode would not exhibit this; drawing it in magic will be the lesser issue the.... {Attachments} 2026-09_media/image-1B26A.png [2026-09-08 8:41 p.m.] namibj This is a 3-finger min-size-the-device-generator-in-klayout-accepts schottky; the upper m1 bar joins the anodes and from all I can tell the cathodes are just well taps for the dnwell [2026-09-08 8:47 p.m.] namibj {Attachments} 2026-09_media/sc_diodex241-27C9E.mag 2026-09_media/sc_diode1-F175B.mag [2026-09-08 9:09 p.m.] namibj I think I've hit oscillation behavior; capped it at what's only a couple minutes of simulation time, and re-running now to get a valid formatted rawfile out for xschem to look at [2026-09-08 9:41 p.m.] tholin Magic is NOT enjoying this {Attachments} 2026-09_media/image-62C77.png [2026-09-08 9:41 p.m.] tholin Weird DRC errors [2026-09-08 9:55 p.m.] tholin What? What is this? {Attachments} 2026-09_media/image-989F2.png [2026-09-08 9:55 p.m.] tholin This seems broken [2026-09-08 9:57 p.m.] tholin Yeah, magic... did not parse that one correctly, I think [2026-09-08 10:07 p.m.] tholin After all this, it turns out that schottkys are not available as medium voltage devices [2026-09-08 10:07 p.m.] tholin 3.3V only [2026-09-08 10:09 p.m.] tholin I think, ideally, I need a way for this to not use diodes {Attachments} 2026-09_media/image-D8E42.png [2026-09-08 10:09 p.m.] tholin DISABLE is a digital input. I can find another way to implement it. [2026-09-08 10:09 p.m.] tholin But CTRL has to be analog [2026-09-08 10:09 p.m.] tholin Essentially, the circuit is supposed to do a `max(CURREF, CTRL)` [2026-09-08 10:09 p.m.] tholin CURREF limits current, CTRL limits voltage [2026-09-08 10:11 p.m.] tholin On an empty cell, CURREF is going to be the thing limiting the PFETs as the cell is sinking so much power, the voltage regulator would have to turn the PFETs up way too much to raise the voltage. But eventually, the cell fills up, and the current is enough to raise the voltage, and now the voltage regulator has to kick in. [2026-09-08 10:12 p.m.] tholin Wait a second [2026-09-08 10:13 p.m.] tholin Instead of having a single block of power PFETs like this {Attachments} 2026-09_media/image-0D0E3.png [2026-09-08 10:13 p.m.] tholin What if I just put two power PFETs in series? {Attachments} 2026-09_media/image-554DC.png [2026-09-08 10:13 p.m.] tholin One under control of the current limiter and the other under control of the voltage regulator? [2026-09-08 10:14 p.m.] tholin Both can limit the flow of electricity. The current that ends up making it all the way through is determined by the lesser of the two. [2026-09-08 10:15 p.m.] tholin That would require me to edit my power PFET layout to be set up this way, and each stage would half in size [2026-09-08 10:15 p.m.] tholin But I think it’d still be capable of putting through 1A [2026-09-08 10:16 p.m.] tholin @namibj Would this work? The only thing I can imagine messing this up is oscillations right at the boundary where the current limiter and voltage regulator fight with each other. [2026-09-08 10:16 p.m.] namibj don't [2026-09-08 10:19 p.m.] namibj > Schottky_diode layer can exist both in LV or MV area. https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_10_14.html > Model vs EP Nominal Target > sc_diode (W/L/m) > > =(0.62u/20u/4) > Model > > BV (V) I_leak (nA/um^2) Von (V) BV I_leak (V) (nA/um^2) Von (V) > Min -10 - 0.22 - - - > Typ -17 35 0.32 -17.6 31 0.32 > Max - 200 0.42 - - - [2026-09-08 10:20 p.m.] namibj ok fine [2026-09-08 10:20 p.m.] namibj ideally do some sort of softmax action; not sure how that's best implemented in asic here tho [2026-09-08 10:20 p.m.] tholin ? [2026-09-08 10:21 p.m.] tholin Ok, then, magic is refusing to extract them [2026-09-08 10:21 p.m.] namibj like should just ideally smoothly blend at the transition instead of overshooting either controller's op-amps to beyond their linear range [2026-09-08 10:21 p.m.] namibj @Tim Edwards [2026-09-08 10:22 p.m.] namibj Pretty sure the shottky_diode behavior doesn't care about thin vs. thick oxide zone though [2026-09-08 10:22 p.m.] namibj doesn't involve poly after all [2026-09-08 10:24 p.m.] namibj maybe put large enough capacitors on the anode side of those diodes so they don't get as much opportunity to start ringing between which one of them is winning the control at the moment where the blending action is going on [2026-09-08 10:26 p.m.] namibj XR8, XR6, XC1, FILT, TRIG.... what's that for? {Attachments} 2026-09_media/control-43BC4.png [2026-09-08 10:27 p.m.] namibj end-of-charge? [2026-09-08 10:29 p.m.] tholin {Attachments} 2026-09_media/image-8EB30.png [2026-09-08 10:30 p.m.] tholin Yes [2026-09-08 10:30 p.m.] tholin It has a low-pass filter on it so transients from the oscillations don’t trigger it [2026-09-08 10:33 p.m.] namibj huh [2026-09-08 10:33 p.m.] tholin I mean, the diodes are a hassle in general. They break ngspice, they have some strange reverse leakage and they have a voltage drop because they’re diodes, making it even harder for both the voltage reg or the current limiter to do their jobs. [2026-09-08 10:33 p.m.] namibj can you show me `lol.gds`? [2026-09-08 10:33 p.m.] tholin {Attachments} 2026-09_media/lol-2BB87.mag [2026-09-08 10:33 p.m.] tholin Its a mag file [2026-09-08 10:34 p.m.] tholin I’m pretty sure I messed it up, though, because it claims A and K are electrically shorted [2026-09-08 10:34 p.m.] namibj yeah please mint a gds for me if you can [2026-09-08 10:34 p.m.] namibj oh it opened it looks non-terrible at least [2026-09-08 10:35 p.m.] namibj ok the shottkey zone should be larger [2026-09-08 10:36 p.m.] namibj it should be contained in the dnwell but the shottkey zone should fully cover all the diffusions and contacts other than the guardring [2026-09-08 10:36 p.m.] tholin {Attachments} 2026-09_media/sc_diode.klay-C8DEB.gds [2026-09-08 10:38 p.m.] tholin One thing I don’t understand is how this doesn’t short both anode and cathode to ground? Because, the deep n-well is contacting the n-well, so its also grounded. [2026-09-08 10:38 p.m.] tholin I’m not sure what’s going on here [2026-09-08 10:39 p.m.] namibj also the diffusions for anode that are not the outer ones because those can't be anode are comp but NOT nplus [2026-09-08 10:39 p.m.] namibj there is no pplus other than the guard ring at all [2026-09-08 10:39 p.m.] namibj yeah it's a contact on comp without plus diffusion, and that's why it's a shottkey junction that's formed [2026-09-08 10:40 p.m.] tholin Oh, I see [2026-09-08 10:40 p.m.] tholin I think I know what I need to do to fix this [2026-09-08 10:41 p.m.] namibj this looks good [2026-09-08 10:41 p.m.] tholin Yeah, but the way magic parses it is messed up [2026-09-08 10:41 p.m.] tholin {Attachments} 2026-09_media/image-7B370.png 2026-09_media/image-F1728.png [2026-09-08 10:41 p.m.] namibj there's no nwell, only the dnwell. substrate is psub. [2026-09-08 10:42 p.m.] namibj yikes, welp [2026-09-08 10:42 p.m.] tholin Oh my god. I... swapped nwell and pwell/substrate in my head again, as usual. [2026-09-08 10:42 p.m.] namibj I mean drawing a finger that's legal shouldn't be too hard [2026-09-08 10:42 p.m.] tholin Yeah, I understand now [2026-09-08 10:42 p.m.] namibj the anode in the middle of the two cathodes need to not extend beyond the cathode [2026-09-08 10:42 p.m.] tholin I’m not sure how its SUPPOSED to be, is the problem [2026-09-08 10:42 p.m.] namibj gaps can be larger than what the klayout example has [2026-09-08 10:43 p.m.] namibj can't you draw comp without pplus nplus or gate? [2026-09-08 10:44 p.m.] tholin No [2026-09-08 10:45 p.m.] tholin According to opening the .mag file in a text editor, this in the box here is "schottkyc". A special contact layer. Maybe that’s it? {Attachments} 2026-09_media/image-8CF6D.png [2026-09-08 10:47 p.m.] tholin Nope [2026-09-08 10:48 p.m.] namibj ok I can't find any structure that has that... huh, weird indeed. [2026-09-08 10:48 p.m.] namibj yeah let's wait with the drawing of it in magic for tim to respond [2026-09-08 10:51 p.m.] tholin I would still like to see if I can re-design this circuit to not require diodes [2026-09-08 10:52 p.m.] namibj {Attachments} 2026-09_media/image-61EA4.png [2026-09-08 10:54 p.m.] namibj {Attachments} 2026-09_media/control_bench.raw-E3088.zst [2026-09-08 10:55 p.m.] namibj is that from the discharge resistor on the battery simulating capacitor vs. the lack of sufficcient input hysteresis action on the voltage limit / end-of-charge comparators? [2026-09-08 10:57 p.m.] tholin I think that should be the discharge resistor [2026-09-08 10:58 p.m.] namibj I mean you can have, ignoring the comparatively trivial matter of dealing with the digital disable function, it such that the current limit providing op-amp does the needed pull-down action to turn the gate as much on as that aspect would like, and then you take a series transistor to limit this drive strength if the voltage limit is reached [2026-09-08 10:59 p.m.] namibj all against a static pull-up or something that looks like a depletion-load.... like, I mean, it can be a resistor or a constant current pull-up [2026-09-08 11:04 p.m.] namibj Great network fail again 🙁 [2026-09-08 11:06 p.m.] namibj Welp, mpv still works even if my desk keyboard choked and I can't easily fix that now.... [2026-09-08 11:25 p.m.] tholin This almost works {Attachments} 2026-09_media/image-874CB.png [2026-09-08 11:25 p.m.] tholin Its just an analog adder [2026-09-08 11:26 p.m.] tholin The hope is that the voltage reg can add additional voltage to the control signal to restrict it further [2026-09-08 11:26 p.m.] tholin But in order to do that, I have to replace a comparator in `control` with an opamp {Attachments} 2026-09_media/image-DBC03.png [2026-09-08 11:26 p.m.] tholin And these are not rail-to-rail [2026-09-08 11:26 p.m.] tholin So the less than 1V it outputs breaks the adder. [2026-09-08 11:27 p.m.] tholin I just can not escape the diodes [2026-09-08 11:44 p.m.] tholin Wait, I just did it [2026-09-08 11:45 p.m.] tholin This is working with way more minimal oscillations (the compout oscillations were rail-to-rail before) {Attachments} 2026-09_media/image-8B748.png [2026-09-08 11:45 p.m.] tholin I... how? [2026-09-08 11:46 p.m.] tholin My ~~code~~ schematic works, and I don’t know why [2026-09-08 11:46 p.m.] tholin Pushed to my repo [2026-09-08 11:47 p.m.] tholin I’m going to bed, my brain can’t handle more weirdness today [2026-09-08 11:52 p.m.] tholin Charge complete detection is broken, I’ll get to it later. [2026-09-09 12:58 a.m.] namibj for the disable action you can then further (if the current limit machinery may stay on during the disable event) put a digital pass gate/transmission gate between the output of this and the gate power driver, and hard-clamp-pull-up the gate to turn it as off as can be. [2026-09-09 1:00 a.m.] namibj Look at the gate capacitance of the power FET and see what RC time constant you're getting there with the drive strength to it. Might have to look at what voltage gain you're expecting out of it too as that'll bump the gain bandwidth product up by that gain [2026-09-09 1:00 a.m.] namibj or down if you have sub-unity voltage gain as I'd expect it to do under LDO operating conditions!!! [2026-09-09 1:01 a.m.] namibj you should be able to set up for the adder to operate in only the say center third of the rail-to-rail range and just simple voltage divider inputs and output-feedback to that very range [2026-09-09 1:03 a.m.] namibj you don't need rail to rail output at any place, you only need the final drive to have enough range to cover the desired operating conditions of your power FET; use appropriate resistor-divider-scaled feedback to map it to the control signals inside. [2026-09-09 1:06 a.m.] namibj silicon p[i]n diodes have a lil weird behavior due to their reverse recovery charge; though not too unliklely the mere rectifying could have already done it. [2026-09-09 1:07 a.m.] namibj remember the feedback to the `COMPOUT` is blocked off as far as DC flow goes when the diode is biased blocking.... and AC impedance is gonna be much different between forward biased and reverse biased conditions. [2026-09-09 1:08 a.m.] namibj oh great I'll try to check it out and look at where specifically the oscillation originates from there. [2026-09-10 12:24 a.m.] tholin Pushed again. Charge complete detection now works again. ============================================================== Exported 363 message(s) ==============================================================